1. Field of the Invention
The present invention relates to module-testing devices for testing a module to be evaluated (hereinafter, referred to as “the module”). The module is a circuit device with features for a predetermined purpose, such as an RF (Radio Frequency) module, a sensor module including a sensor and an accessory circuit thereof, or a radar module for forward acquisition, or other suitable circuit device.
2. Description of the Related Art
A known module-testing device will be described with reference to FIG. 6. FIG. 6 shows a construction of a module-testing device 40 that tests an RF module of a portable phone.
The RF module 42 performs signal processing in an RF band. The RF module 42 is, for example, a frequency synthesizer or a variable gain amplifier (hereinafter, referred to as “a component to be controlled”) that is controlled in response to a digital control signal. When the RF module 42 is mounted in the portable phone, the control signal fed to the component to be controlled is output from a control circuit of the portable phone.
The module-testing device 40 includes a module tester 44 and a module control circuit 46. The module-testing device 40 realizes operations of the RF module 42 that is virtually implemented when the RF module 42 is at a developing stage, so that an operation test of the RF module 42 can be performed. The module control circuit 46 is mounted along with, for example, the RF module 42 on a testing substrate 48. A printed circuit pattern disposed on the testing substrate 48 allows the RF module 42 and the module control circuit 46 to be electrically connected.
The module tester 44 feeds a test signal, such as the RF reception signal or an IQ transmission signal (orthogonal signal), to the RF module 42 where predetermined processing, such as frequency conversion processing or amplification processing between the RF signal and the IQ signal, is applied to the test signal, which is fed back to the module tester 44. On the basis of the resultant signal, the module tester 44 determines whether the RF module 42 appropriately operates. The module control circuit 46 controls the module tester 44.
The module control circuit 46 produces a control signal (i.e. testing control signal) for controlling the components to be controlled in the RF module 42. In other words, the module control circuit 46 controls the module tester 44 and the components to be controlled of the RF module 42 to realize various virtual operating environments (test modes).
The specifications of the RF module 42 often vary in accordance with the model of the portable phone on which the RF module 42 is mounted. In addition, the specifications may be modified during the development of the RF module 42 (pre-production lot). Since the module control circuit 46 controls the components to be controlled of the RF module 42, whenever the specifications of the RF module 42 are modified, another module control circuit 46 must be provided or the module control circuit 46 must be updated so as to accommodate the modification in the specifications.
In view of the above-described circumstances, programmable logic devices (hereinafter, referred to as PLD), such as FPGA (Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device), have been used. The PLD is a circuit that is capable of realizing various features by changing internal circuit components thereof. By adopting PLD as the module control circuit 46, the module control circuit 46 can be shared for tests of a plurality of RF modules with different specifications. Devices for simulation analysis with the aid of FPGA are disclosed in, for example, Japanese Unexamined Patent Application Publication No. 10-63704 and Japanese Unexamined Patent Application Publication No 2001-186011.
An input/output signal assignment for the input/output pins of the PLD (that is, the input/output positions of the PLD signals) is determined in accordance with a circuit construction (circuit arrangement) built inside the PLD. When, for example, a circuit L1 is constructed at an early stage of a construction process of the module control circuit (PLD) 46, desired signal input/output positions Pi1, and Po2 can be obtained as shown in FIG. 7. However, as the construction process of the module control circuit (PLD) 46 progresses, existing circuits constructed in the module control circuit (PLD) 46 may restrict input/output positions of a newly assigned circuit. When, for example, a circuit Ln shown in FIG. 7 is constructed, even though a desired signal output position is a pin Poa, the presence of existing circuits L1 to Ln−1 in the module control circuit (PLD) 46 causes the signal output position to not be the pin Poa but a pin pon. In particular, the larger the circuits built in the module control circuit (PLD) 46, the fewer the number of the unused gates of the module control circuit (PLD) 46, making it more difficult to assign input/output signals to desired corresponding input/output pins.
Since the printed circuit pattern between the RF module 42 and the module control circuit (PLD) 46 establishes electrical connection between the respective input/output pins thereof, the printed circuit pattern must be produced so that the input/output signal assignment thereof corresponds to the input/output pins of the PLD (module control circuit 46). When the construction of the module control circuit (PLD) 46 in accordance with the specifications of each RF module 42 causes the signal input/output positions of the printed circuit pattern between the RF module 42 and the module control circuit (PLD) 46 to be varied, the printed circuit pattern must be produced separately so as to accommodate each module control circuit (PLD) 46. In other words, even though the PLD is adopted as the module control circuit 46 to intend to be shared for testing different RF modules, the printed circuit pattern between the RF module 42 and the module control circuit 46 is often difficult to be shared. Producing the printed circuit pattern individually leads to lengthening the development time and increasing the labor and the cost involved in the development.